Zilog Z16C35 - Manual (Page 87)

ISCC
User Manual
UM011002-0808
81
delay, and doesn’t be-gin transmitting until it receives the second EOP. There are also two
additional status bits in RR10, the On Loop bit and the Loop Sending bit.
There are also restrictions as to when and how a secondary station physically becomes part
of the loop.
A secondary station that has just powered up must monitor the loop, without the one-bit-
time delay, until it recognizes an EOP. When an EOP is recognized the one-bit-time de-lay
is switched on. This does not disturb the loop because the line is marking idle between the
time that the controller sends the EOP and the time that it receives the EOP back. The sec-
ondary station that has gone on-loop cannot place a message on the loop until the next
time that an EOP is issued by the controller. A secondary station goes off-loop in a similar
manner. When given a command to go off-loop, the secondary station waits until the next
EOP to remove the one-bit-time delay.
To operate the ISCC in SDLC Loop mode, the ISCC must first be programmed just as if
normal SDLC were to be used. Loop mode is then selected by writing the appropriate con-
trol word in WR10; the ISCC is now waiting for the EOP so that it can go on loop. While
waiting for the EOP, the ISCC ties TxD to RxD with only the internal gate delays in the
signal path. When the first EOP is recognized by the ISCC, the Break/Abort/EOP bit is set
in RR0, generating an External/Status interrupt (if so enabled). At the same time, the On-
Loop bit in RR10 is set to indicate that the ISCC is indeed on-loop, and a one-bit time
delay is inserted in the TxD to the RxD path.
The ISCC is now on-loop but cannot transmit a message until a flag and the next EOP are
received. The requirement that a flag be received ensures that the ISCC cannot errone-
ously send messages until the controller ends the current polling sequence and starts
another one.
If the CPU in the secondary station with ISCC needs to transmit a message, the Go-
Active-On-Poll bit in WR10 must be set. If this bit is set when the EOP is detected, the
ISCC changes the EOP to a flag and starts sending another flag. The EOP is reported in
the Break/Abort/EOP bit in RR0 and the CPU should write its data bytes to the ISCC, just
as in normal SDLC frame transmission. When the frame is complete and CRC has been
sent, the ISCC closes with a flag and reverts to One-Bit-Delay mode. The last zero of flag,
along with the marking line echoed from the RxD pin, form an EOP for secondary stations
further down the loop.
While the ISCC is actually transmitting a message, the loop-sending bit in R10 is set to
indicate this.
If the Go-Active-On-Poll bit is not set at the time the EOP passes by, the ISCC cannot
send a message until a flag (terminating the current polling sequence) and another EOP are
received.
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