Zilog Z16C35 - Manual (Page 136)

ISCC
User Manual
UM011002-0808
130
5.6 DMA CELL REGISTER DESCRIPTIONS
5.6.1 Channel Command/Address Register
This register is a write only register and is at the same address as the DMA Status Register.
Figure 5-26 shows the bit positions for this register.
Bits 7 through 5 are encoded with the commands for the DMA as shown below:
Bit combination 000 is a Null command and has no affect on the DMA.
Bit combination 001 is reserved
Bit combination 010 is the DMA Reset Highest IUS command. This command resets only
the highest priority IUS bit that is set in the DMA cell and occurs independent of the state
of the IEI for the ISCC.
Bit combination 011 is the Reset command and is used to reset the DMA cell. All of the
DMA channels are reset. The DMA channels remain reset until enabled.
Bit combination 100 is the command to enable the Transmitter B channel DMA. The
DMA operation is not triggered by this command.
Figure 5–55. Channel Command/Address Register
Bit combination 101 is the command to enable the Receiver B channel DMA. The DMA
operation is not triggered by this command.
Null Command
Reserved
Reset Highest IUS
DMA Reset
Enable Tx B DMA
Enable Rx B DMA
Enable Tx A DMA
Enable Rx A DMA
Address: 00000 (Write)
D6 D7 D5 D4 D3 D2 D1 D0
Address 0
Address 1
Address 2
Address 3
Address 4
0
0
1
1
0
0
1
1 0
1
0
1
0
1
0
1 0
0
0
0
1
1
1
1
DMA Commands
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