Zilog Z16C35 - Manual (Page 23)

ISCC
User Manual
UM011002-0808
17
fer or until the terminal count is reached, or /BUSACK is deactivated. The four DMA
channels operate independently when the Request Per Channel option is selected; other-
wise, all requests pending at the time of bus acquisition will be serviced before the bus is
released. Each DMA channel is independently enabled and disabled.
2.4 REGISTER ACCESS
ISCC registers may be accessed explicitly, directly or indirectly. Explicit addressing
occurs only for three registers in the ISCC: these are the Bus Configuration Register (for
the first write after a hardware reset), the RDR (Receive Data Register) by a fly-by DMA
read, and the TDR (Transmit Data Register) by a fly-by DMA write. In the non-multi-
plexed bus case, only WR0/RR0 of the SCC cell and only the Channel Command/Address
Register of the DMA cell are accessed directly. Other registers are accessed using the
pointers in these directly accessed registers. In the multiplexed bus case, all registers
(except the WR0, RR0 and CCAR) are accessed through a two step address/read-write bus
transaction. In this case there are two options available for address decoding: shift right
and shift left. These options are independently selectable for both the SCC cell and the
DMA cell.
2.4.1 SCC Cell Register Access, Multiplexed Bus
The registers in the ISCC in the multiplexed bus mode are addressed via the address on
AD7-AD0 which is latched by the rising edge of /AS. As discussed in the paragraphs
below, the address contains a bit to select the SCC cell channel (A or B). Although this
selection is in the address, the A1/A//B input remains active and must be set to select
Channel A for the selection bit in the AD7-AD0 address to function correctly. Conversely,
the A1/A//B pin may also be used to select the channel instead of the bit in the AD7-AD0
address. In this case, the bit in the AD7-AD0 address must be set to select Channel A for
the A1/A//B input to function correctly.
There are two address decoding modes: shift left and shift right. In shift left mode, the reg-
ister address is decoded from AD5-AD1. This mode is set by a hardware reset.
In the shift left mode, the register address itself is placed on AD4-AD1 and the Channel
Select bit, A/B, is decoded from AD5. The register map for this case is shown in
Table 2-2.
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