Zilog Z16C35 - Manual (Page 79)

ISCC
User Manual
UM011002-0808
73
Underrun Latch can be read in RR0. The Tx Underrun Latch may be reset by the processor
via WR0.
For correct transmission of the CRC at the end of a frame, the Reset Tx Underrun/EOM
Latch command must be issued after the first character is written to the ISCC but before
the transmitter underruns after the last character written to the ISCC. The command is usu-
ally issued immediately after the first character is written to the ISCC so that the abort or
CRC is sent if an underrun occurs inadvertently. The Abort/Flag on Underrun bit (D2) in
WR10 is usually set to “1” at the same time as the Tx Underrun/EOM bit is reset so that an
abort can still be sent if the transmitter underruns. The Abort/Flag on Underrun bit is then
set to “0” near the end of the frame to allow the correct transmission of CRC.
In this paragraph the term “completely sent” means shifted out of the Transmit Shift regis-
ter, not shifted out of the zero inserter, which is an additional five bit times of delay. In
SDLC mode, if the transmitter is disabled during transmission of a character, that charac-
ter will be “completely sent”. This applies to both data and flags. However, if the
trans-mitter is disabled during the transmission of CRC, 16 total bits corresponding to the
two CRC bytes will be transmitted but part of the bits will be from the CRC generator and
the latter part of the bits will be from the Flag register rather than form the CRC generator.
Thus part of the CRC bytes will not be transmitted.
There are two modem control signals associated with the transmitter provided by the
ISCC.
The /RTS pin is a simple output that carries the inverted state of the RTS bit (D1) in WR5.
The /CTS pin is ordinarily a simple input to the CTS bit in RR0. However, if Auto Enables
mode is selected this pin becomes and enable for the transmitter. That is, if Auto Enables
is ON and the /CTS pin is High the transmitter is disabled. If the /CTS pin is Low, the
transmitter is enabled.
The initialization sequence for the transmitter in SDLC mode is: WR4 first, to select the
mode, then WR10 to modify it if necessary, WR7 to program the flag, and then WR3 and
WR5 to select the various options. At this point the other registers should be initialized as
necessary. When all of this is complete, the transmitter may be enabled by setting bit D3 of
WR5 to “1”. Now that the transmitter is enabled, the CRC generator may be initialized by
issuing the Reset Tx CRC Generator command in WR0. A summary is shown in Table 4-
11.
Table 4–19. Initializing the Transmitter in SDLC Mode
Register Bit No Description
WR5 5-6 Number of bits per character
WR4 1-0 Select parity
WR5 2 Select CRC-CCITT
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