Zilog Z16C35 - Manual (Page 105)

ISCC
User Manual
UM011002-0808
99
Bit 5 selects Auto Enables
This bit programs the function for both the /DCD and /CTS pins. /CTS becomes the trans-
mitter enable and /DCD becomes the receiver enable when this bit is set to “1.” However,
the Receiver Enable and Transmit Enable bits must be set before the /DCD and /CTS pins
can be used in this manner. When the Auto Enables bit is set to “0,” the /DCD and /CTS
pins are merely inputs to the corresponding status bits in Read Register 0. The state of
/DCD is ignored in the Local Loopback mode. The state of /CTS is ignored in both Auto
Echo and Local Loopback modes.
Bit 4 forces the SCC cell to Enter Hunt Mode
This command forces the comparison of sync characters or flags to assembled receive
characters for the purpose of synchronization. After reset, the ISCC cell automatically
enters the Hunt mode (except asynchronous). Whenever a flag or sync character is
matched, the Sync/Hunt bit in Read Register 0 is reset and, if External/Status Interrupt
Enable is set, an interrupt sequence is initiated. The ISCC automatically enters the Hunt
mode when an abort condition is received or when the receiver is enabled.
Bit 3 is the Receiver CRC Enable
This bit is used to initiate CRC calculation at the beginning of the last byte transferred
from the Receiver Shift register to the receive FIFO. This operation occurs independently
of the number of bytes in the receive FIFO. When a particular byte is to be excluded from
CRC calculation, this bit should be reset before the next byte is transferred to the receive
FIFO. If this feature is used, care must be taken to ensure that eight bits per character is
selected in the receiver because of an inherent delay from the Receive Shift register to the
CRC checker.
This bit is internally set to “1” in SDLC mode and the ISCC calculates CRC on all bits
except inserted zeros between the opening and closing character flags. This bit is ignored
in asynchronous modes.
Bit 2 selects the Address Search Mode (SDLC)
Setting this bit in SDLC mode causes messages with addresses not matching the address
programmed in WR6 to be rejected. No receiver interrupts can occur in this mode unless
there is an address match. The address that the ISCC attempts to match can be unique (1 in
256) or multi-ple (16 in 256), depending on the state of Sync Character Load Inhibit bit.
The Address Search mode bit is ignored in all modes except SDLC.
Bit 1 is the SYNC Character Load Inhibit
If this bit is set to “1” in any mode except SDLC, the ISCC compares the byte in WR6
with the byte about to be stored in the FIFO, and it inhibits this load if the bytes are equal.
(Caution this also occurs in the asynchronous mode if the received character matches the
contents of WR6.) The ISCC does not calculate the CRC on bytes stripped from the data
stream in this manner. If the 6-bit sync option is selected while in Monosync mode, the
compare is still across eight bits, so WR6 must be programmed for proper operation.
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