Zilog Z16C35 - Manual (Page 100)

ISCC
User Manual
UM011002-0808
94
5.4.2 Write Register 1 (Transmit/Receive Interrupt and Data Transfer
Mode Definition)
Write Register 1 is the control register for the various SCC cell interrupt and Wait/Request
modes. Figure 5-3 shows the bit assignments for WR1.
Using Point High Command
Table 5–26. SCC Cell Register Address Map using Pointer (Non-Multiplexed Bus Mode)
Using Null Command
A1/A//B Address D2 D1 D0 Write Register Read Register
0 000 WR0B RR0B
0 001 WR1B RR1B
0 010 WR2 RR2B
0 011 WR3B RR3B
0 100 WR4B (RR0B)
0 101 WR5B (RR1B)
0 110 WR6B (RR2B)
0 111 WR7B (RR3B)
1 000 WR0A RR0A
1 001 WR1A RR1A
1 010 WR2 RR2A
1 011 WR3A RR3A
1 100 WR4A (RR0A)
1 101 WR5A (RR1A)
1 110 WR6A (RR2A)
1 111 WR7A (RR3A)
A1/A//B Address D2 D1 D0 Write Register Read Register
0 000 WR8B RR8B
0 001 WR9 (RR13B)
0 010 WR10B RR10B
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