Zilog Z16C35 - Manual (Page 151)

ISCC
User Manual
UM011002-0808
145
Figure 5–67. Transmit DMA Address Registers (Continued)
5.6.13 Bus Configuration Register
The first write to the ISCC after a hardware reset is always to the Bus Configuration Reg-
ister. The register is shown in Figure 5-38. The Bus Configuration Register is not affected
by any reset function other than a hardware reset and is accessible only after the hardware
reset. Note that when writing to the Bus Configuration Register, /AS and A1/A//B are used
to program certain bus interface features. Refer to the Bus Interface Unit description for
details.
(E)
Address: 11100 (Bits 0-7)
D6 D7 D5 D4 D3 D2 D1 D0
Tx B Addr0
Tx B Addr1
Tx B Addr2
Tx B Addr3
Tx B Addr4
Tx B Addr5
Tx B Addr6
Tx B Addr7
(F)
D6 D7 D5 D4 D3 D2 D1 D0
Tx B Addr8
Tx B Addr9
Tx B Addr10
Tx B Addr11
Tx B Addr12
Tx B Addr13
Tx B Addr14
Tx B Addr15
(G)
Address: 11110 (Bits 16-23)
D6 D7 D5 D4 D3 D2 D1 D0
Tx B Addr16
Tx B Addr17
Tx B Addr18
Tx B Addr19
Tx B Addr20
Tx B Addr21
Tx B Addr22
Tx B Addr23
(H)
Address: 11111 (Bits 24-31)
D6 D7 D5 D4 D3 D2 D1 D0
Address: 11101 (Bits 8-15)
Tx B Addr24
Tx B Addr25
Tx B Addr26
Tx B Addr27
Tx B Addr28
Tx B Addr29
Tx B Addr30
Tx B Addr31
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