Zilog Z16C35 - Manual (Page 59)

ISCC
User Manual
UM011002-0808
53
The additional parity bit per character is transferred to the receive data FIFO along with
the data if the data plus parity is eight bits or less. The Parity Error bit in the receive error
FIFO may be programmed to cause a special receive condition interrupt by setting bit D2
of WR1 to “1”. This error bit is latched and so will remain active, once set, until an Error
Reset command has been issued. If interrupts are not used to transfer data, the Parity Error,
Framing Error, and Overrun Error bits in RR1 should be checked before the data is
removed from the receive data FIFO.
The ISCC™ may be programmed to accept a receive clock that is one, sixteen, thirty-two,
or sixty-four times the data rate. This is selected by bits D7 and D6 in WR4. The 1X mode
is used when bits are synchronized external to the receiver. The 1X mode is the only mode
in which a data encoding method other than NRZ may be used. The clock factor is com-
mon to the receiver and transmitter.
The ISCC provides up to three modem control signals associated with the receiver.
The /SYNC pin is a general-purpose input whose state is reported in the Sync/Hunt bit in
RR0. If the crystal oscillator is enabled, this pin is not available and the Sync/Hunt bit is
forced to “0”. Otherwise, the /SYNC pin may be used to carry the Ring Indicator signal.
The /DTR//REQ pin carries the inverted state of the DTR bit (D7) in WR5 unless this pin
has been programmed to carry a DMA Request signal.
The /DCD pin is ordinarily a simple input to the DCD bit in RR0. However, if the Auto
Enables mode is selected by setting D5 of WR3 to “1”, this pin becomes an enable for the
receiver. That is, if Auto Enables is on and the /DCD pin is High, the receiver is disabled.
While the /DCD pin is Low, the receiver is enabled.
The break condition is continuous “0s”, as opposed to the usual continuous ones during an
idle. The ISCC recognizes the Break condition upon seeing a null character (all “0s”) plus
a framing error. Upon recognizing this sequence the Break bit in RR0 will be set and will
remain set until a “1” is received. At this point the break condition is no longer present. At
the termination of a break the receive data FIFO contains a single null character, which
should be read and discarded. The Framing Error bit will not be set for this character, but
if odd parity has been selected, the Parity Error bit will be set. Caution should be exercised
if the receive data line contains a switch that is not debounced to generate breaks. Switch
bounce may cause multiple breaks, recognized by the ISCC to be additional characters
assembled in the receive data FIFO. It may also cause a receive overrun condition being
latched.
Received characters are assembled, checked for errors, and moved to a three byte FIFO.
When there is at least one character in the FIFO the Rx Character Available bit (in RR0) is
set to 1 and, optionally, an interrupt or DMA request can be generated. Since errors apply
to specific characters, it is necessary that error information moves along side the data that
it refers to. This is implemented in the ISCC with a three entry error FIFO in parallel with
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