Zilog Z16C35 - Manual (Page 34)

ISCC
User Manual
UM011002-0808
28
3.2.2 Transmitter DMA Operation
With the DMA enabled, the status of an empty transmitter FIFO triggers the DMA to
request the bus and begin DMA transfer to the transmit FIFO. Once this DMA channel is
selected for service, DMA transfers continue until the transmit FIFO is full (or until termi-
nal count is reached if there are not enough bytes remaining to fill the FIFO). Once started,
the DMA for the channel continues until the FIFO is full even though a request from a
higher priority DMA channel arises. Upon completion of the current DMA channel ser-
vice, the next highest priority DMA channel commences its operation. The ISCC contin-
ues to hold the bus until all pending DMA requests have been served. Note that if the Bus
Request Per Channel option has been selected, then the bus will be released and subse-
quently re-requested for each channel. At the completion of the block transfer (terminal
count reached), an interrupt will be generated, if enabled. If selected, the interrupt vector
will indicate the interrupt source according to Table 3-1.
An Interrupt Pending only modifies the interrupt vector if the corresponding Interrupt
Enable bit is set. Note that software may have to test status bits to determine if the channel
interrupt is due to terminal count or an abort.
Note that the DMA request will follow the state of the transmit FIFO even though the
transmitter is disabled. Thus, if the DMA is enabled, the DMA may write data to the SCC
cell before the transmitter is enabled. This will not cause a problem in Asynchronous
mode but may cause problems in Synchronous mode because the ISCC will send data in
preference to flags or sync characters. Thus a data character in the transmit FIFO may get
transmitted prior to the frame sync character or opening flag. It may also complicate the
CRC initialization, which cannot be done until after the transmitter is enabled. DMA
requests essentially follow the Tx Buffer Empty bit in the SCC cell Read Register 0.
3.3 BAUD RATE GENERATOR
The Baud Rate Generator (BRG) is essential for asynchronous communications. Each
channel in the ISCC contains a programmable baud rate generator. Each generator consists
of two 8-bit, time-constant registers forming a 16-bit time constant, a 16-bit down counter,
and a flip-flop on the output that makes the output a square wave. On start-up, the flip-flop
on the output is set High, so that it starts in a known state, the value in the time-constant
register is loaded into the counter, and the counter begins counting down. When a count of
zero is reached, the output of the baud rate generator toggles, the value in the time-con-
stant register is loaded into the counter, and the process starts over. A block diagram of the
baud rate generator is shown in Figure 3-1.
The time-constant can be changed at any time, but the new value does not take effect until
the next load of the counter (i.e., after zero count is reached).
No attempt is made to synchronize the loading of a new time-constant with the clock used
to drive the generator.
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