2 architecture -7, 2 architecture – Maxim Integrated MAXQ7666 User Manual
Page 9
1.2 Architecture
The MAXQ7665/MAXQ7666 architecture is designed to be modular and expandable. Top-level instruction decoding is extremely sim-
ple and based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into
the system register and peripheral register groups. Figure 1-2 illustrates the modular architecture and the basic transport possibilities.
MAXQ7665/MAXQ7666 User’s Guide
1-7
SYSTEM MODULES/
REGISTERS
PERIPHERAL MODULES/REGISTERS
DATA
MEMORY
dst
STACK
MEMORY
CKCN
WDCN
IC
ADDRESS
GENERATION
IP
SP
IC
LOOP COUNTERS
LC[
η]
IIR
IMR
INTERRUPT
LOGIC
CLOCK CONTROL,
WATCHDOG TIMER
AND POWER MONITOR
BOOLEAN
VARIABLE
MANIPULATION
ACCUMULATORS
(16)
AP
APC
PSF
INSTRUCTION
DECODE
(SRC, DST TRANSPORT
DETERMINATION)
MUX
DATA POINTERS
DP[0], DP[1]
FP =
(BP + OFFS)
DPC
SC
MEMORY MANAGEMENT
UNIT (MMU)
PROGRAM
MEMORY
src
dst
src
GENERAL-
PURPOSE
I/O
TIMERS/
COUNTERS
UART
AND SPI
CAN
ANALOG
I/0
HARDWARE
MULTIPLIER
JTAG
DEBUG
ENGINE
Figure 1-2. MAXQ7665/MAXQ7666 Transport-Triggered Architecture
Maxim Integrated