Maxim Integrated MAXQ7666 - Manual (Page 293)

MAXQ7665/MAXQ7666 User’s Guide
10-7
10.4.2 Run-Test-Idle
As illustrated in Figure 10-2, the run-test-idle state is an intermediate state for getting to one of the two state sequences in which the
TAP controller performs meaningful operations:
• Controller state sequence (IR-scan)
• Data register state sequence (DR-scan)
10.4.3 IR-Scan Sequence
The MAXQ7665/MAXQ7666 support a 3-bit TAP instruction register to allow certain device specific instructions (e.g., "Debug" or
"System Programming") to be supported. The IR-Scan sequence allows instructions (e.g., "Debug" and "System Programming") to be
shifted into the instruction register starting from the select-IR-scan state. In the TAP, the instruction register is connected between the
TDI input and the TDO output. Inside the IR-scan sequence, the capture-IR state loads a fixed binary pattern (001b) into the 3-bit shift
register and the shift-IR state causes shifting of TDI data into the shift register and serial output to TDO, least significant bit first. Once
the desired instruction is in the shift register, the instruction can be latched into the parallel instruction register (IR2:IR0) on the falling
edge of TCK in the update-IR state. The contents of the 3-bit instruction shift register and parallel instruction register (IR2:IR0) are sum-
marized with respect to the TAP controller states in Table 10-2.
When the parallel instruction register (IR2:IR0) is updated, the TAP controller decodes the instruction and performs any necessary
operations, including activation of the data shift register to be used for the particular instruction during data register shift sequences
(DR-scan). The length of the activated shift register depends upon the value loaded to the instruction register (IR2:IR0). The support-
ed instruction register encodings and associated data-register selections are shown in Table 10-3.
The extest (IR2:IR0 = 000b) and sample/preload (IR2:0 = 001b) instructions are mandated by the JTAG standard; however, the
MAXQ7665/MAXQ7666 do not make use of these instructions. These instructions are treated as no operations and may be entered into
the instruction register without affecting the on-chip system logic or pins and does not change the existing serial data register selection
between TDI and TDO.
The bypass (IR2:IR0 = 011b, 101b, or 111b) instruction is also mandated by the JTAG standard. The bypass instruction is fully imple-
mented by the MAXQ7665/MAXQ7666 to provide a minimum length serial data path between the TDI and the TDO pins. This is accom-
plished by providing a single-cell bypass shift register. When the instruction register is updated with the bypass instruction, a single
bypass register bit is connected serially between TDI and TDO in the shift-DR state. The instruction register automatically defaults to
the bypass instruction when the TAP is in the test-logic-reset state. The bypass instruction has no effect on the operation of the on-chip
system logic.
The debug (IR2:IR0 = 010b) and system programming (IR2:IR0 = 100b) instructions are private instructions that are intended solely
for in-circuit debug and in-system programming operations, respectively. If the instruction register is updated with the debug instruc-
tion, a 10-bit serial shift register is formed between the TDI and TDO pins in the shift-DR state. If the system programming instruction
is entered into the instruction register (IR2:IR0), a 3-bit serial data shift register is formed between the TDI and TDO pins in the shift-
DR state.
Instruction register (IR2:IR0) settings other than those listed and previously described are reserved for internal use. As can be seen in
Figure 10-1, the instruction register serves to select the length of the serial data register between TDI and TDO during the shift-DR state.
Table 10-2. Instruction Register Content vs. TAP Controller State
TAP CONTROLLER STATE INSTRUCTION SHIFT REGISTER PARALLEL (3-BIT) INSTRUCTION REGISTER (IR2:IR0)
Test-Logic-Reset Undefined Set to bypass (011b) instruction
Capture-IR Load 001b at the rising edge of TCK Retain last state
Shift-IR
Input data via TDI and shift towards TDO at the rising
edge of TCK
Retain last state
Exit1-IR, Exit2-IR, Pause-IR Retain last state Retain last state
Update-IR Retain last state Load from shift register at the falling edge of TCK
All other states Undefined Retain last state
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