Maxim Integrated MAXQ7666 - Manual (Page 8)

1.1.2 Instruction Set
As part of the MAXQ family, the MAXQ7665/MAXQ7666 use the standard 16-bit MAXQ20 instruction set, with all instructions a fixed 16
bits in length. A register-based, transport-triggered architecture allows all instructions to be coded as simple transfer operations. All
instructions reduce to either writing an immediate value to a destination register or memory location or moving data between registers
and/or memory locations.
This simple top-level instruction decoding allows all instructions to be executed in a single cycle. Since all CPU operations are per-
formed on registers only, any new functionality can be added by simply adding new register modules. The simple instruction set also
provides maximum flexibility for code optimization by a compiler.
1.1.3 Harvard Memory Architecture
As part of the MAXQ family, the MAXQ7665/MAXQ7666 core architecture is based on the MAXQ20 design, which implements a 16-bit
internal databus and ALU. Program memory, data memory, and register space on the MAXQ7665/MAXQ7666 follow the Harvard archi-
tecture model. Each type of memory is kept separate and is accessed by a separate bus, allowing different word lengths for different
types of memory. Registers may be either 8 or 16 bits in width. Program memory is 16 bits in width to accommodate the standard MAXQ
16-bit instruction set. Data memory is also 16 bits in width but can be accessed in 8-bit or 16-bit modes for maximum flexibility.
The MAXQ7665/MAXQ7666 include a flexible memory management unit (MMU), which allows code to be executed from either the pro-
gram flash, the utility ROM, or the internal data SRAM. Any of these three memory spaces may also be accessed in data space at any
time, with the single restriction that whichever physical memory area is currently being used as program space cannot be read from
in data space.
1.1.4 Register Space
Since all functions in the MAXQ family are accessed through registers, common functionality is provided through a common register
set. Many of these registers provide the equivalent of higher level op codes by directly accessing the arithmetic logic unit (ALU), the
loop counter registers, and the data pointer registers. Others, such as the interrupt registers, provide common control and configura-
tion functions that are equivalent across all MAXQ microcontrollers.
The common register set, also known as the System Registers, includes the following:
• ALU access and control registers, including working accumulator registers and the processor status flags
• Two Data Pointers and a Frame Pointer for data memory access
• Auto-decrementing Loop Counters for fast, compact looping
• Instruction Pointer and other branching control access points
• Stack Pointer and an access point to the 16-bit-wide dedicated hardware stack
• Interrupt vector, identification, and masking registers
The MAXQ7665/MAXQ7666 peripheral register space (modules 0 to 5) contains registers that access the following peripherals:
• General-purpose, 8-bit, I/O port (P0)
• Serial UART interface
• Serial peripheral interface (SPI)
• Hardware multiplier
• JTAG debug engine
• Three programmable Type 2 timer/counters
• Controller area network (CAN) interface
• Analog input/output module
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