Maxim Integrated MAXQ7666 - Manual (Page 183)

MAXQ7665/MAXQ7666 User’s Guide
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4.6 Initializing the CAN Controller
Software initialization of the CAN controller begins with the setting of the software initialization bit (SWINT) in the CAN 0 control periph-
eral register. When SWINT = 1, the CAN module is disabled and the CAN transmit output (CANTXD) is placed in a recessive state.
This, in turn, allows the microcontroller to write information into the CAN MOVX SRAM control/status/mask registers without the possi-
bility of corrupting data transmissions or receptions in progress. Setting SWINT does not clear the receive- and transmit-error counters,
but allows the microcontroller to write a common value to both error counters through the CAN 0 transmit-error peripheral register. See
the description of the SWINT bit for specifics of the software initialization process.
All CAN registers located in the peripheral register map, with the exception of the CAN 0 control register, are cleared to 00h following
a system reset. The CAN 0 control register is set to 09h following a system reset. CAN registers located in the dual port memory map
are indeterminate following a system reset. A system reset also clears both the receive- and transmit-error counters in the CAN con-
troller, takes the CAN processor offline, and sets the SWINT bit in the CAN 0 control register.
Following a reset, the CAN-related registers in Table 4-2 must be initialized for proper operation of the CAN module. These registers
are in addition to specific registers associated with mask, format, or specific message centers.
Table 4-2. Registers to Be Initialized for Proper CAN Module Operation
4.7 CAN Interrupts
The CAN processor is assigned an interrupt that is individually enabled via the C0IE bit in the EIE register and globally enabled/dis-
abled by the IM4 bit in the IMR register and the IGE bit in the IC peripheral register. A CAN 0 interrupt can be generated by either a
receive/transmit acknowledgment from one of the 15 message centers or by a change in the CAN 0 status register.
CAN 0 transmit/receive interrupt sources are derived from a successful transmit or receive of data within one of the 15 message cen-
ters as signaled by the INTRQ bit in the associated CAN 0 message (1–15) control register. Each message center (1–15) provides a
separate receive interrupt enable (ERI) and transmit interrupt enable (ETI) bits in the respective CAN 0 message (1–15) control regis-
ter to allow setting of the INTRQ bit in response to successful transmission or reception. The CAN 0 interrupt register (C0IR) can then
be used to determine which message center generated the interrupt request. Software must clear the respective INTRQ bit in the asso-
ciated CAN 0 message (1–15) control register to clear the interrupt source before leaving the interrupt routine.
The CAN 0 interrupt source can also be connected to a change in the CAN 0 status register. Each of the bits in the CAN 0 status reg-
ister represents a potential source for the interrupt. To simplify the application and testing of a device, these sources are broken into
two groups that, for interrupt purposes, are enabled separately by the ERIE and STIE bit of the CAN 0 control (C0C) register. This allows
the nonstandard errors typically associated with development to be grouped under the STIE enable. These include the successful
receive RXS, successful transmit TXS, wake status WKS, and general set of error conditions reported by ER2:ER0. Also note that since
the RXS and TXS bit are cleared by software, if a second message is received or transmitted before the RXS or TXS bits are cleared
and after a read of the CAN 0 status register, a second interrupt is generated. The remaining error sources comprise the BSS and
EC96/128 bits in the CAN 0 status register. These read-only bits are separately enabled via the ERIE bit in the CAN 0 control register.
A read of the CAN 0 status register is required to clear either of the two groups of error interrupts. It is possible that multiple changes
to the status register can occur before the register is read. In that case, the status register generates only one interrupt. Figure 4-12
provides a graphical illustration of the interrupt sources and their respective interrupt enables.
REGISTER SIGNIFICANCE
C0BT0, C0BT1
(Dual Port Address 02h(L), 02h(H))
These dual port control registers must be set to configure CAN 0 bus timing. The exact values are
dependent on the network configuration and environment.
COR (Module 4, Index 5) C0BPR7, C0BPR6 (COR.4, COR3) must be configured as part of the CAN 0 bus timing.
Maxim Integrated