Maxim Integrated MAXQ7666 - Manual (Page 144)

MAXQ7665/MAXQ7666 User’s Guide
4-14
CAN 0 Extended Global Mask Register 1 (C0EGM1)
CAN 0 Extended Global Mask Register 2 (C0EGM2)
CAN 0 Extended Global Mask Register 3 (C0EGM3)
CAN 0 Extended Global Mask Registers 0 to 3 (C0EGM0 to COEGM3). These registers function as the mask when performing the
extended global identification test (EX/
ST = 1) when message ID masking is enabled (MEME = 1) for message centers 1–14. When
EX/ ST = 0 or MEME = 0 for a given message center, the contents of this register are ignored. These registers can only be modified
during a software initialization (SWINT = 1).
When EX/ ST = 1, the 29 bits of the message ID are compared against the 29 bits of the CAN message center arbitration registers,
using the 29 bits of the CAN extended global mask registers as a mask. Any bit in the extended global mask registers set to 0 ignores
the state of the corresponding bit in the incoming message ID field when performing the test. Any bit in the extended global mask reg-
isters set to 1 forces the state of the corresponding bit in the incoming message ID field and CAN message center arbitration regis-
ters 0–3 to match before considering the incoming message a match.
The three least significant bits in the C0EGM3 are not used and do not perform any comparison of these bit locations. A read of these
bits always returns 0, and writes to these bits are ignored.
Programming all mask registers to 00h effectively disables the global ID test for that message, accepting all messages. As such, the
global mask registers act as a don’t care following a system reset.
Bit # 7 6 5 4 3 2 1 0
Name MASK20 MASK19 MASK18 MASK17 MASK16 MASK15 MASK14 MASK13
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Dual Port
Address
04h(H)
Bit # 7 6 5 4 3 2 1 0
Name MASK12 MASK11 MASK10 MASK9 MASK8 MASK7 MASK6 MASK5
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Dual Port
Address
05h(L)
Bit # 7 6 5 4 3 2 1 0
Name MASK4 MASK3 MASK2 MASK1 MASK0 — — —
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Dual Port
Address
05h(H)
r = read, w = write (allowed only when SWINT = 1 via C0DP/C0DB)
Maxim Integrated