3 tap interface control -5, 1 system control register (sc) -5, 3 tap interface control – Maxim Integrated MAXQ7666 User Manual
Page 291: 1 system control register (sc)
10.3 TAP Interface Control
Once an application has been loaded and starts running, the MAXQ7665/MAXQ7666 JTAG TAP interface can be controlled by the TAP
bit in the system control register as described in Section 10.3.1.
10.3.1 System Control Register (SC)
Register Description:
System Control Register
Register Name:
SC
Register Address:
Module 08h, Index 08h
Bit 7: Test Access (JTAG) Port Enable (TAP). This bit controls whether the TAP special function pins are enabled. The TAP defaults
to being enabled.
0 = JTAG/TAP functions are disabled and P0.0–P0.3 can be used as general-purpose I/O pins
1 = TAP special function pins P0.0–P0.3 are enabled to act as JTAG inputs and outputs
Bits 6 and 0: Reserved.
Bits 5 and 4: Code Data Access Bits 1 and 0 (CDA1:CDA0). See
Section 1 for more information on these bits.
Bit 3: Upper Program Access (UPA). See
Section 1 for more information on this bit.
Bit 2: ROM Operation Done (ROD). See
Section 11 for more information on this bit.
Bit 1: Password Lock (PWL). See
Section 12 for more information on this bit.
MAXQ7665/MAXQ7666 User’s Guide
10-5
Bit #
7
6
5
4
3
2
1
0
Name
TAP — CDA1
CDA0 UPA ROD PWL —
Reset 1 0 0 0 0 0 1* 0
Access
rw
r
rw
rw
rw
rw
rw
r
r = read, w = write
*
This register defaults to 80h on all forms of reset except after power-on reset. After power-on reset, the PWL bit is also set and this register defaults to 82h.
Maxim Integrated