Maxim Integrated MAXQ7666 User Manual

Page 159

MAXQ7665/MAXQ7666 User’s Guide

4-29

The INTIN vector value does not change when a new interrupt source becomes active and the previous one has not yet been acknowl-
edged and removed (i.e., microcontroller read of CAN 0 status register or microcontroller clear of the appropriate INTRQ bit in the
respective CAN 0 message control register), regardless of the fact that the new interrupt has a higher priority or not.

If two properly enabled interrupt sources become active at the same time, the interrupt of highest priority is indicated. For example, if
a message center completes a successful transmission or reception and both STIE and ERI, ETI are set, the interrupt indicated by the
INTIN7:INTIN0 vector is that of the status-change interrupt (i.e., INTIN7 = 01h and not the message center interrupt; i.e., INTIN7:INTIN0
= MCV.

RXS and TXS are always activated when a transmission or reception is successfully completed. These bits are reset by the microcon-
troller writing 0 to them. Reading the CAN 0 status register only removes the INTIN7:INTIN0 = 01h vector, but does not clear these bits.
These bits (RXS and TXS) can be set by either the CAN processor or microcontroller, but are never reset by the CAN controller.

The CAN 0 interrupt is active when an active interrupt source is indicated in the interrupt vector INTIN7:INTIN0. Changes in the
INTIN7:INTIN0 value from a previous 00h state indicate the interrupt source first detected by the CAN processor following the nonac-
tive-interrupt state. The INTIN7:INTIN0 interrupt values displayed in C0IR remain in place until the respective interrupt source is
removed, independent of other higher (or lower) priority interrupts that become active prior to clearing the currently displayed interrupt
source. The CAN 0 interrupt to the microcontroller is not active when INTIN7:INTIN0 = 00h. In all the other cases, the interrupt line is
asserted and the INTIN7:INTIN0 vector must be read to determine the current interrupt source.

When the current (INTIN7:INTIN0) interrupt source is cleared, INTIN7:INTIN0 is changed to reflect the next active interrupt with the
highest priority. The status-change interrupt is asserted if there has been a change in the CAN 0 status register (if enabled by the
appropriate ERIE and/or STIE bit) and the CAN status interrupt state is set. A message center interrupt is indicated if the INTRQ bit in
the respective CAN message control register is set.

The priority of the next interrupt displayed is fixed. For example, consider the case when the current INTIN7:INTIN0 value is that of a
message center interrupt. The current INTIN7:INTIN0 interrupt source is cleared (INTRQ = 0), and the status-change interrupt and
another message center interrupt are both active. The next interrupt indicated by INTIN7:INTIN0 would be the status-change interrupt
that has a higher priority than that of the message center interrupt.

When the current INTIN7:INTIN0 interrupt indicated is a status interrupt and the status register is read, the INTIN7:INTIN0 vector is
changed to the next lowest INTIN7:INTIN0 value (which is the next highest priority) of the corresponding message center whose INTRQ
bit is set to 1. During this time the interrupt line to the microcontroller remains active. The microcontroller either does an RETI and is
then forced back into the same interrupt routine via the active interrupt line, or it remains in the interrupt routine until the microcontroller
has cleared all active interrupt sources (INTIN7:INTIN0 = 00h).

An active message center interrupt is cleared by writing 0 to the INTRQ bit in the respective CAN message control register. The inter-
rupt line to the microcontroller goes to an inactive state and the INTIN7:INTIN0 vector resets to 00h if there are no other interrupts active
and enabled.

Example Case:

t: moment in time

STIE = 1, ERI = 1, ETI = 1

t1: INTRQ[1] = 1, RXS = 1