Maxim Integrated MAXQ7666 - Manual (Page 266)

8.2.2 External Interrupt Flag Register (Port 0) (EIF0)
Register Description: External Interrupt Flag Register (Port 0)
Register Name: EIF0
Register Address: Module 00h, Index 03h
Bits 15 to 8: Reserved. Read returns 0, write ignored.
Bit 7: Bit 7 Edge Detect (IE7). This bit is set when a negative edge (IT7 = 1) or a positive edge (IT7 = 0) is detected on the interrupt
7 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must
be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set. Note
that this flag register simply indicates whether an edge has been detected at port 0 and is not affected by the state of EIE0.
Bit 6: Bit 6 Edge Detect (IE6). This bit is set when a negative edge (IT6 = 1) or a positive edge (IT6 = 0) is detected on the interrupt
6 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must
be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set. Note
that this flag register simply indicates whether an edge has been detected at port 0 and is not affected by the state of EIE0.
Bit 5: Bit 5 Edge Detect (IE5). This bit is set when a negative edge (IT5 = 1) or a positive edge (IT5 = 0) is detected on the interrupt
5 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must
be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set. Note
that this flag register simply indicates whether an edge has been detected at port 0 and is not affected by the state of EIE0.
Bit 4: Bit 4 Edge Detect (IE4). This bit is set when a negative edge (IT4 = 1) or a positive edge (IT4 = 0) is detected on the interrupt
4 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must
be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set. Note
that this flag register simply indicates whether an edge has been detected at port 0 and is not affected by the state of EIE0.
Bit 3: Bit 3 Edge Detect (IE3). This bit is set when a negative edge (IT3 = 1) or a positive edge (IT3 = 0) is detected on the interrupt
3 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must
be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set. Note
that this flag register simply indicates whether an edge has been detected at port 0 and is not affected by the state of EIE0.
MAXQ7665/MAXQ7666 User’s Guide
8-4
r = read, w = write
Note: This register is cleared to 00h on all forms of reset.
Bit # 15 14 13 12 11 10 9 8
Name — — — — — — — —
Reset 0 0 0 0 0 0 0 0
Access r r r r r r r r
Bit # 7 6 5 4 3 2 1 0
Name IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
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