Maxim Integrated MAXQ7666 - Manual (Page 19)

• The utility ROM can be accessed as data with offset at 8000h.
• One page (byte access mode) or two pages (word access mode) can be accessed as data with offset at 0000h as determined
by the CDA1:0 bits.
1.2.3.7 Data Alignment
To support merged program and data memory operation while maintaining efficiency on memory space usage, the data memory must
be able to support both byte-wide and word-wide accessing. Data is aligned in data memory as word, but the effective data address is
resolved to bytes. This data alignment allows direct program fetching in its native word size while maintaining accessibility at the byte
level. It is important to realize that this accessibility requires strict word alignment. All executable words must align to an even address
in byte mode. Care must be taken when updating the code segment in the unified data memory space as misalignment of words will
likely result in loss of program execution control. Worst yet, this situation may not be detected if the watchdog timer is also disabled.
Data memory is organized as two byte-wide memory banks with common word address decode but two 8-bit data buses. The data
memory will always be read as a complete word, independent of operation, whether program fetch or data access. The program
decoder always uses the full 16-bit word, whereas the data access can utilize a word or an individual byte.
In byte mode, data pointer hardware reads out the word containing the selected byte using the effective data word address pointer
(the least significant bit of the byte data pointer is not initially used). Then, the least significant data pointer bit functions as the byte
select that is used to place the target byte to the data path. For write access, data pointer hardware addresses a particular word using
the effective data word address while the least significant bit selects the corresponding data bank for write, leaving the contents of the
other memory bank unaffected.
1.2.3.8 Memory Management Unit
Memory allocation and accessing control for program and data memory can be managed by the memory management unit (MMU). A
single memory management unit option is discussed in this user’s guide, however the memory management unit implementation for
any given product depends upon the type and amount of memory addressable by the device. Users should consult the individual prod-
uct data sheet(s) and/or user’s guide supplement(s) for detailed information.
Although supporting less than the maximum addressable program and data memory segments, the MMU implementation presented
provides a high degree of programming and access control flexibility. It supports the following:
• User program memory up to 32k x 16 (up to 64k x 16 with inclusion of UPA bit).
• Utility ROM up to 8k x 16.
• Data memory SRAM up to 16k x 16.
• In-system and in-application programming of embedded EEPROM, flash, or SRAM memories.
• Access to any of the three memory areas (SRAM, code memory, utility ROM) using the data memory pointers.
• Execution from any of the three memory areas (SRAM, code memory, factory written and tested utility-ROM routines).
Given these capabilities, the following rules apply to the memory map:
• A particular memory segment cannot be simultaneously accessed as both program and data.
• The offset address is A000h when logically mapping data memory into the program space.
• The offset for logically mapping the utility ROM into the data memory space is 8000h.
• Program memory:
- The lower half of the program memory (P0 and P1) is always accessible, starting at 0000h.
- The upper half of the program memory (P2 and P3) must be activated by setting the UPA bit to 1 when accessing for code
execution, starting at 8000h.
- Setting the UPA bit to 1 disallows access to the utility ROM and logical data memory as program.
- Physical program memory pages (P0, P1, P2, P3) are logically mapped into data space based upon the memory segment
currently being used for execution, selection of byte/word access mode, and CDA1:0 bit settings (described in the Pseudo-
Von Neumann Memory Map and Pseudo-Von Neumann Memory Access sections).
• Data memory
- Access can be either word or byte.
- All 16 data pointer address bits are significant in either access mode (word or byte).
MAXQ7665/MAXQ7666 User’s Guide
1-17
Maxim Integrated