Maxim Integrated MAXQ7666 - Manual (Page 227)

6.3 Modes of Operation
A detailed description of the MAXQ7665/MAXQ7666 UART modes is given in this section.
6.3.1 UART Mode 0
This mode is used to communicate in synchronous, half-duplex format with devices that accept the MAXQ7665/MAXQ7666 micro-
controller as a master. Figure 6-3 shows a functional block diagram and basic timing of this mode. As can be seen, there is one bidi-
rectional data line (URX) and one shift clock line (UTX) used for communication. Mode 0 requires that the MAXQ7665/MAXQ7666 be
the master since it generates the serial shift clock for data transfers that occur in either direction.
The URX signal is used for both transmission and reception. Data bits enter and exit least significant bit first. The UTX pin provides the
shift clock. The baud rate is equal to the shift clock frequency. When not using power management mode, the baud rate in mode 0 is
equivalent to the system clock divided by either 12 or 4, as selected by the SM2 bit in the SCON0 register.
The UART begins transmitting when a write is performed to SBUF0. The internal shift register then begins to shift data out. The clock
is activated and transfers data until the 8-bit value is complete. Data is presented one clock prior to the falling edge of the shift clock
(UTX) so that an external device can latch the data using the rising edge of the shift clock.
The UART begins to receive data when the REN bit in the SCON0 register (SCON0.4) is set to logic 1 and the RI bit (SCON0.0) is set
to logic 0. This condition indicates that there is data to be shifted in on the URX pin. The shift clock (UTX) is activated and data is
latched on the rising edge. The external device should, therefore, present data on the falling edge. This process continues until all 8
bits have been received. The RI bit is automatically set to logic 1, one clock cycle following the last rising edge of the shift clock on
UTX. This causes reception to stop until SBUF0 has been read and the RI bit cleared. When RI is cleared, another byte can be shift-
ed in, if available.
6.3.2 UART Mode 1
This mode provides asynchronous, full-duplex communication. A total of 10 bits is transmitted, consisting of a start bit (logic 0), 8 data
bits, and 1 stop bit (logic 1), as illustrated in Figure 6-4. The data is transferred least significant bit first. The baud rate is programma-
ble through the baud-clock generator and is discussed in
Section 6.4.
Following a write to SBUF0, the UART begins transmission five clock cycles after the first baud clock from the baud-clock generator.
Transmission takes place on the UTX pin. It begins with the start bit being placed on the pin. Data is then shifted out onto the pin, least
significant bit first. The stop bit follows. The TI bit is set by hardware after the stop bit is placed on the pin. All bits are shifted out at
the rate determined by the baud-clock generator.
Once the baud-clock generator is active, reception can begin at any time. The REN bit (SCON0.4) must be set to logic 1 to allow recep-
tion. The detection of a falling edge on the URX pin is interpreted as the beginning of a start bit, and will begin the reception process.
Data is shifted in at the selected baud rate. At the middle of the stop bit time, certain conditions must be met to load SBUF0 with the
received data in the receive shift register:
RI must = 0, and either
if SM2 = 0, the state of the stop bit does not matter
or
if SM2 is 1, the state of the stop bit must be 1
If these conditions are true, SBUF0 will be loaded with the received byte, the RB8 bit (SCON0.2) is loaded with the stop bit, and the RI
bit (SCON0.0) is set. If these conditions are false, then the received data is lost (SBUF0 and RB8 not loaded) and RI is not set.
Regardless of the receive word status, after the middle of the stop bit time, the receiver goes back to looking for a 1-to-0 transition on
the URX pin.
Each data bit received is sampled on the 7th, 8th, and 9th clock used by the divide-by-16 counter. Using majority voting, two equal
samples out of the three determine the logic level for each received bit. If the start bit was determined to be invalid (= 1), then the
receive logic goes back to looking for a 1-to-0 transition on the URX pin in order to start the reception of data.
MAXQ7665/MAXQ7666 User’s Guide
6-9
Maxim Integrated