Maxim Integrated MAXQ7666 - Manual (Page 259)

MAXQ7665/MAXQ7666 User’s Guide
7-24
7.4.3 Measure Period
To measure the period of the signal seen on the T0 input pin, the Type 2 timer is configured for a single-shot capture, no gating, either
edge (selected by the CCF1:CCF0 bits). The CPRL2 bit can be set to generate a reload on each capture edge.
; ------------------ Reset State: T2R0 = T2V0 = T2C0 = 0000h ------------------------
MOVE T2CFG0, #00000100b ;
; T2DIV[2:0] =000 (/1)
; T2MD =0 (16-bit)
; CCF[1:0] =10 (falling edge)
; C/T2 =0 (timer/capture)
MOVE T2CNA0, #10000110b ; ET2 =1 (enable Timer ints)
; T2OE0 =0 (input)
; T2POL0 =0 (gating level = ‘0’)
; TR2L:TR2 =00 (don’t start timer )
; CPRL2 =1 (reload on capture edge)
; SS2 =1 (single shot mode)
; G2EN =0 (gating disabled)
; ------------------ TCC2 Interrupt : PERIOD = T2C0
T0 PIN
CODE EXECUTION:
POINT A
CODE EXECUTION:
POINT B
1A 2A
1B 2B
EVENTS:
1A: FALLING EDGE CAUSES CAPTURE/RELOAD; SINGLE-SHOT CAPTURE CYCLE BEGINS.
2A: FALLING EDGE CAUSES CAPTURE/RELOAD; SINGLE-SHOT CAPTURE CYCLE ENDS; PERIOD = T2C0.
1B AND 2B: SAME SEQUENCE AS 1A–2A, EXCEPT THAT THE SINGLE-SHOT CAPTURE CYCLE DOES NOT BEGIN UNTIL THE FIRST FALLING EDGE IS DETECTED.
Figure 7-8. Type 2 Timer Application Example—Measure Period
Maxim Integrated