Maxim Integrated MAXQ7666 - Manual (Page 284)

9.3.3 SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted and received over two serial data lines with respect to a single serial shift
clock. The polarity and phase of the serial shift clock are the primary components in defining the SPI data transfer format. The polarity
of the serial clock corresponds to the idle logic state of the clock line and therefore also defines which clock edge is the active edge.
To define a serial shift clock signal that idles in a logic-low state (active clock edge = rising), the clock polarity select (SPICF.0: CKPOL)
bit should be configured to 0, while CKPOL = 1 causes the shift clock to idle in a logic-high state (active clock edge = falling). The
phase of the serial clock selects which edge is used to sample the serial shift data. The clock phase select (SPICF.1:CKPHA) bit con-
trols whether the active or inactive clock edge is used to latch the data. When CKPHA is set to logic 1, data is sampled on the inactive
clock edge (clock returning to the idle state). When CKPHA is set to logic 0, data is sampled on the active clock edge (clock transition
to the active state). Together, the CKPOL and CKPHA bits allow the four possible SPI data transfer formats as illustrated in Figure 9-3.
Anytime that the active clock edge is used for sampling (CKPHA = 0), the transfer cycle must be started with assertion of the SS sig-
nal. This requirement necessitates that the SS signal be deasserted and reasserted between successive transfers. Conversely, when
the inactive edge is used for sampling (CKPHA = 1), the SS signal may remain low through successive transfers allowing the active
clock edge to signal the start of a new transfer.
MAXQ7665/MAXQ7666 User’s Guide
9-11
Figure 9-3. SPI Transfer Formats (CKPOL, CKPHA Control)
SCLK
CKPOL = 0
CKPHA = 0
CKPOL = 0
CKPHA = 1
CKPOL = 1
CKPHA = 0
CKPOL = 1
CKPHA = 1
MOSI/MISO
SS
SAMPLING POINTS
TRANSFER CYCLE (CHARACTER LENGTH DEFINED BY CHR)
MSBIT LSBIT
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