Maxim Integrated MAXQ7666 - Manual (Page 168)

MAXQ7665/MAXQ7666 User’s Guide
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Bit 3: External Transmit Request (EXTRQ). (Read/clear only.) When EXTRQ is cleared to 0, there are no pending requests by exter-
nal CAN nodes for this message. When EXTRQ is set to 1, a request has been made for this message by an external CAN node, but
the service request has not been completed by the CAN 0 controller at the time of the read of EXTRQ. Following the completion of a
requested transmission by a message center programmed for transmission (T/
R = 1), the EXTRQ bit is cleared by the CAN 0 controller.
A remote request is only answered by a message center programmed for transmission (T/ R = 1) when DTUP = 1 and TIH = 0 (i.e.,
when new data was loaded and is not being currently modified by the microcontroller). Note that a message center programmed for
a receive mode (T/
R = 0) also detects a remote frame request and sets the EXTRQ bit in a similar manner, but does not automatically
transmit a data frame and, as such, does not automatically clear the EXTRQ bit.
Bit 2: Microcontroller Transmit Request (MTRQ). MTRQ is unrestricted read and can only be set to 1 when written to by the micro-
controller. A write of 0 to MTRQ leaves the MTRQ bit unchanged. MTRQ can only be cleared as a result of a successful transmission
by the respective message center, or when the CRST bit is set or the CAN processor experiences a system reset from the reset sources
outlined in the functional description in the reset option and reset timing section of this user’s guide.
The MTRQ is a read, limited-write bit, and is designed to allow the microcontroller to request a message to be transmitted. MTRQ is
programmed to 1 when the microcontroller is requesting the respective message to be transmitted. MTRQ remains set until such time
that the message transmission is successfully completed, at which time the CAN 0 controller clears the MTRQ bit. Setting MTRQ with
T/
R = 1 (directional = transmit) results in the sending of a data frame for the transmitted message, and setting MTRQ with T/R = 0
(directional = receive) results in the sending of a remote frame request. When the associated message is programmed for transmit (T/ R
= 1), the MTRQ bit is also set by the CAN 0 controller at the same time that the EXTRQ bit is set by a message request from an exter-
nal node. MTRQ is cleared by the CAN 0 controller at the same time as the EXTRQ bit, once a successful transmission of the message
is completed. Note that the MTRQ bit located in message center 15 is ignored by the CAN processor, since message center 15 is a
receive-only message center.
Bit 1: Receive Overwrite/Transmit Inhibit (ROW/TIH). The ROW and TIH bits share the same bit 1 location in the CAN 0 message
control register. The ROW function is only supported when the associated message is programmed via the T/
R = 0 bit in the message
format register to function in the receive mode. Similarly, the TIH function is only supported when the associated message is pro-
grammed via the T/
R = 1 bit in the message format register to function in the transmit mode.
Receive Overwrite (ROW). (T/ R = 0, read-only.) The CAN 0 controller automatically sets the ROW bit to 1 if a new message
is received and stored while the DTUP bit was still set. When set, ROW indicates that the previous message was potentially
lost and may not have been read, since the microcontroller had not cleared the DTUP bit prior to the new load. When ROW
= 0, no new message has been received and stored while DTUP was set to 1 since this bit was last cleared. Note that the
ROW bit is not set when the WTOE bit is cleared to 0, since all overwrites are disabled. Thus, if the incoming message match-
es the respective message center and DTUP = 1 in the respective message center, the combination of WTOE = 0 and DTUP
= 1 forces the CAN processor to ignore the respective message center when the CAN is processing the incoming data.
The CAN processor clears ROW when the microcontroller clears the DTUP bit associated with the same message center. It
must be pointed out that the ROW bit for message center 15 is related to the overwrite of the buffer associated with message
center 15, as opposed to the actual message center 15. ROW reflects the actual message center relationships for message
centers 1–14. The ROW bit for the message center 15 shadow buffer is cleared once the shadow buffer is loaded into mes-
sage center 15, and the shadow buffer is cleared to allow a new message to be loaded. The shadow buffer is automatically
loaded into message center 15 when the microcontroller clears the DTUP and EXTRQ bits in message center 15.
Transmit Inhibit (TIH). (T/ R = 1, unrestricted read/write.) The TIH bit allows the microcontroller to disable the transmission of
the message when the data contents of the message are being updated. TIH = 1 directs the CAN 0 controller not to transmit
the associated message. TIH = 0 enables the CAN 0 controller to transmit the message. If TIH = 1, EXTRQ is set to 1 when
a remote frame request is received by the message. Following the remote frame request and after the microcontroller has
established the proper data to be sent, the microcontroller clears the TIH bit to 0, allowing the CAN processor to send the
data requested by the previous remote frame request. Note that the TIH bit located in message center 15 is ignored by the
CAN processor, since message center 15 is a receive-only message center.
If the message center being set up with WTOE = 1 was previously a transmit message center, ensure that the TIH bit is cleared
to 0. (TIH can only be written while T/
R is set to 1.) If TIH is set to 1 and that message center is changed to receive with WTOE
= 1, the ROW bit always reads back 1, even though a receive overwrite condition may not have occurred.
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