Maxim Integrated MAXQ7666 - Manual (Page 230)

MAXQ7665/MAXQ7666 User’s Guide
6-12
6.3.3 UART Mode 2
This mode uses a total of 11 bits in asynchronous, full-duplex communication as illustrated in Figure 6-5. The 11 bits consist of one
start bit (logic 0), 8 data bits, a programmable 9th bit, and one stop bit (logic 1). Like mode 1, the transmissions occur on the UTX sig-
nal pin and receptions on URX.
For transmission purposes, the 9th bit can be stuffed as logic 0 or 1. A common use is to put the parity bit in this location. The 9th bit
is transferred from the TB8 bit position in the SCON0 register following a write to SBUF0 to initiate a transmission. The UART transmis-
sion begins five clock cycles after the first rollover of the divide-by-16 counter following a software write to SBUF0. It begins with the
start bit being placed on the UTX pin. The data is then shifted out onto the pin, least significant bit first, followed by the 9th bit, and
finally the stop bit. The TI bit is set when the stop bit is placed on the pin.
Once the baud-rate generator is active and the REN bit has been set to logic 1, reception can begin at any time. Reception begins
when a falling edge is detected as part of the incoming start bit on the URX pin. The URX pin is then sampled according to the baud
rate speed. The 9th bit is placed in the RB8 bit location of the SCON0 register. At the middle of the 9th bit time, certain conditions must
be met to load SBUF0 with the received data:
RI must = 0, and either
if SM2 = 0, the state of the 9th bit does not matter
or
if SM2 is 1, the state of the 9th bit must be 1
If these conditions are true, SBUF0 will be loaded with the received byte, the RB8 bit is loaded with the 9th bit, and the RI bit is set. If
these conditions are false, then the received data is lost (SBUF0 and RB8 not loaded) and RI is not set. Regardless of the receive word
status, after the middle of the stop bit time, the receiver goes back to looking for a 1-to-0 transition on the URX pin.
Data is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples. Mode 2 uses the sample divide-
by-16 counter with either the system clock divided by 2 or 4, thus resulting in a baud clock of either system clock/32 or system clock/64.
6.3.4 UART Mode 3
This mode has the same operation as mode 2, except for the baud-rate source. As shown in Figure 6-6, mode 3 generates the baud rates
through the baud-clock generator. The bit shifting and protocol are the same. The baud-clock generator is discussed in
Section 6.4.
Maxim Integrated