Maxim Integrated MAXQ7666 - Manual (Page 313)

11.3.6 Read-Register Map Command Host-ROM Instruction
A read-register map command reads out data contents for all implemented system and peripheral registers. The host does not specify
a target register but instead should expect register data output in successive order, starting with the lowest order register in register mod-
ule 0. Data is loaded by the ROM to the 8-bit ICDB register and is output one byte per transfer cycle. Thus, for a 16-bit register, two trans-
fer cycles are necessary. The host initiates each transfer cycle to shift out the data bytes and will find valid data output tagged with a
debug-valid (status = 11b). At the end of each transfer cycle, the debug engine clears the TXC flag to signal the ROM service routine
that another byte can be loaded to ICDB. The ROM service routine sets the TXC flag each time after loading data to the ICDB register.
This process is repeated until all registers have been read and output to the host. The host system recognizes the completion of the reg-
ister read when the status debug-idle is presented. This indicates that the debug engine is ready for another operation.
11.3.7 Single-Step (Trace) Operation
The debug engine supports single-step operation in debug mode by executing a trace command from the host. The debug engine
allows the CPU to return to its normal program execution for one cycle and then forces a debug mode re-entry:
1) Set status to 10b (debug-busy).
2) Pop the return address from the stack.
3) Set the IGE bit to logic 1 if debug mode was activated when IGE = 1.
4) Supply the CPU with an instruction addressed by the return address.
5) Stall the CPU at the end of the instruction execution.
6) Block the next instruction fetch from program memory.
7) Push the return address onto the stack.
8) Set the contents of IP to 8010h.
9) Clear the IGE bit to 0 to disable the interrupt handler.
10) Halt CPU operation.
11) Set the status to debug-idle.
Note that the trace operation uses a return address from the stack as a legitimate address for program fetching. The host must main-
tain consistency of program flow during the debug process. The instruction pointer is automatically incremented after each trace oper-
ation, thus a new return address is pushed onto the stack before returning the control to the debug engine. Also, note that the inter-
rupt handler is an essential part of the CPU and a pending interrupt could be granted during single-step operation since the IGE bit
state present on debug mode entry is restored for the single step.
11.3.8 Return
To terminate the debug mode and return the debug engine to background mode, the host must issue a return command to the debug
engine. This command causes the following actions:
1) Pop the return address from the stack.
2) Set the IGE bit to logic 1 if debug mode was activated when IGE = 1.
3) Supply the CPU with an instruction addressed by the return address.
4) Allow the CPU to execute the normal user program.
5) Set the status to 00b (nondebug).
To prevent a possible endless-breakpoint matching loop, no break occurs for a breakpoint match on the first instruction after returning
from debug mode to background mode. Returning to background mode also enables all internal timer functions.
MAXQ7665/MAXQ7666 User’s Guide
11-17
Maxim Integrated