Artesyn ATCA-7480 Installation and Use (February 2015) User Manual
Atca-7480
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Table of contents
Document Outline
- ATCA-7480
- Contents
- About this Manual
- Safety Notes
- Sicherheitshinweise
- Introduction
- Hardware Preparation and Installation
- Controls, Indicators, and Connectors
- Functional Description
- 4.1 Block Diagram
- 4.2 Processor
- 4.3 DDR4 Main Memory
- 4.4 Platform Controller Hub (PCH) Intel C612 Wellsburg
- 4.5 ATCA Fabric IF Ethernet
- 4.6 Storage Controller
- 4.7 MO297 SlimSATA Embedded Solid State Disc (SSD) Carrier/Riser Card
- 4.8 Heat Sink
- 4.9 BIOS
- 4.10 IPMC
- 4.11 Serial Redirection
- 4.12 Serial Over LAN
- 4.13 Control Logic
- 4.14 Front Board Faceplate
- 4.15 Faceplate Serial Interfaces
- 4.16 USB 3.0 Interfaces
- 4.17 LPC Interface
- 4.18 Trusted Platform Module
- 4.19 Real Time Clock
- 4.20 SMBus
- Maps and Registers
- 5.1 FPGA Registers
- 5.1.1 Register Decoding
- 5.1.2 POST Code Register
- 5.1.3 Super IO Configuration Register
- 5.1.4 UART1 and UART2 Register Map
- 5.1.5 FPGA Register Mapping
- 5.1.6 Module Identification Register
- 5.1.7 Version Register
- 5.1.8 Serial Redirection Control Register
- 5.1.9 Serial over LAN (SOL) Control Register
- 5.1.10 Serial Line Routing Register
- 5.1.11 IPMC Power Failure Registers
- 5.1.12 Reset Registers
- 5.1.12.1 BIOS Reset Source Register
- 5.1.12.2 Reset Mask Register
- 5.1.12.3 BIOS IPMC Watchdog Timeout Register
- 5.1.12.4 BIOS Push Button Enable Register
- 5.1.12.5 OS Reset Source Register
- 5.1.12.6 OS IPMC Watchdog Timeout Register
- 5.1.12.7 IPMC Watchdog Timeout Register
- 5.1.12.8 IPMC Reset Source Register
- 5.1.12.9 IPMC Interrupt Status Register
- 5.1.12.10 DIMM ADR Configuration Register
- 5.1.12.11 DIMM ADR Status Register
- 5.1.13 CPU Control Register
- 5.1.14 S-States Control Register
- 5.1.15 NMI Control Status Registers
- 5.1.16 Interrupt Control and Status Registers
- 5.1.17 PCI Express Hot Plug I2C IO Expander Registers
- 5.1.18 Flash Status and Selection Registers
- 5.1.19 PCH Output Enable Register
- 5.1.20 RTM SPI Interface Registers
- 5.1.21 Update Channel Equalization Control Register
- 5.1.22 RTM USB Control Register
- 5.1.23 LED Status and Control Register
- 5.1.24 Spare Signals Status Registers
- 5.1.25 CPU Presence Detection Register
- 5.1.26 CPU Error Status Register
- 5.1.27 Telecom Clock Supervision Registers
- 5.1.28 BIOS Version Registers
- 5.1.29 IPMC BIOS Communication Registers
- 5.1.30 Scratch Registers
- 5.1 FPGA Registers
- BIOS
- 6.1 Introduction
- 6.2 Accessing the Blade Using the Serial Console Redirection
- 6.3 Changing Configuration Settings
- 6.4 Boot Options
- 6.5 IPMI Boot Parameter
- 6.6 BIOS Setup Configuration
- 6.7 UEFI Secure Boot
- 6.8 Restoring BIOS Default Settings
- 6.9 IPMI Support
- 6.10 Watchdog Support
- 6.11 BIOS Error Logging
- 6.12 LED Usage
- 6.13 Upgrading the BIOS
- 6.14 BIOS POST Codes
- Serial Over LAN
- Supported IPMI Commands
- 8.1 Standard IPMI Commands
- 8.2 PICMG 3.0 Commands
- 8.3 Artesyn Embedded Technologies Specific Commands
- 8.4 Pigeon Point Specific Commands
- 8.4.1 Get Status Command
- 8.4.2 Get Serial Interface Properties Command
- 8.4.3 Set Serial Interface Properties Command
- 8.4.4 Get Debug Level Command
- 8.4.5 Set Debug Level Command
- 8.4.6 Get Hardware Address Command
- 8.4.7 Set Hardware Address Command
- 8.4.8 Get Handle Switch Command
- 8.4.9 Set Handle Switch Command
- 8.4.10 Get Payload Communication Time-Out Command
- 8.4.11 Set Payload Communication Time-Out Command
- 8.4.12 Enable Payload Control Command
- 8.4.13 Disable Payload Control Command
- 8.4.14 Reset IPMC Command
- 8.4.15 Hang IPMC Command
- 8.4.16 Graceful Reset Command
- 8.4.17 Get Payload Shutdown Time-Out Command
- 8.4.18 Set Payload Shutdown Time-Out Command
- 8.4.19 Get Module State Command
- 8.4.20 Enable Module Site Command
- 8.4.21 Disable Module Site Command
- 8.4.22 Reset Carrier SDR Repository Command
- IPMI Feature Set
- 9.1 Firmware Architecture
- 9.2 Firmware Upgrade
- 9.3 Sensors
- 9.3.1 Payload Driven Sensors
- 9.3.2 Boot Bank Supervision Sensor
- 9.3.3 IPMC POST Results Sensor
- 9.3.4 Power Good Sensor
- 9.3.5 Power Interface Sensors
- 9.3.6 Reset Cause Sensor
- 9.3.7 Voltage and Temperature Sensor
- 9.3.8 ME Power Failure Sensor
- 9.3.9 Payload Power Failure State Sensor
- 9.3.10 Payload Power Failure Cause Sensor
- 9.4 POST
- 9.5 Ejector Handle De-Bounce
- 9.6 FRU Inventory
- 9.7 Reset and Power Domain
- 9.8 Power Configuration
- 9.9 BIOS Boot Configuration Parameters
- 9.10 Asynchronous Event Notification
- 9.11 Serial Line Selection
- 9.12 BIOS Boot Bank Selection
- 9.13 Glue Logic FPGA Flash Selection
- 9.14 Settable Graceful Shutdown Timeout
- 9.15 Local System Event Log (SEL)
- A Replacing the Battery
- B Related Documentation