Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 131)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 131
5.1.10 Serial Line Routing Register
7:2 Reserved 0 r
Table 5-42 Serial over LAN Control Register
Address Offset: 0x04
Bit Description Default Access
Table 5-43 Serial Line Routing Register
Address Offset: 0x05
Bit Description Default Access
0 Inverted level of signal SEL_SERIAL, which is
controlled by switch SW2.1.
0: COM1 to Faceplate and COM2 to RTM
1: COM1 to RTM and COM2 to Faceplate
Note: Setting may be overwritten by IPMC
Software controlling Bit 4 Ext.
(SW2.1)
0: OFF
1: ON r
1 Inverted level of signal IPMC_SER_2_HEADER,
which is controlled by switch SW2.2
0: IPMC Serial Debug Interface to 3 Pin Header
1: IPMC Serial Debug Interface to Faceplate
Note: Setting may be overwritten by IPMC
Software controlling Bit 5 Ext.
(SW2.2)
0: OFF
1: ON r
3:2 Reserved 0 r
4 IPMC_COM_ROUTE_A
0: COM1 to Faceplate and COM2 to RTM
1: COM1 to RTM and COM2 to Faceplate PWR_GOOD:0 IPMC: r/w
LPC: r
5 IPMC_COM_ROUTE_DEBUG
0: IPMC Serial Debug Interface to 3 Pin Header
1: IPMC Serial Debug Interface to Faceplate PWR_GOOD:0 IPMC: r/w
LPC: r
7:6 Reserved 0 r