Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 100)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 100
5.1.1 Register Decoding
The FPGA registers can be accessed from the host or the IPMC. For the host access, LPC bus
interface is used. The IPMC uses an I2C interface.
5.1.1.1 LPC Decoding
The LPC bus supports different protocols.
5.1.1.1.1 LPC I/O Decoding
The LPC interface responds to LPC I/O accesses listed in the following table. All other LPC I/O
accesses are ignored.
All LPC I/O accesses to address POSTCODE and the address range REGISTERS and within the
address ranges of COM1 or COM2 (only when enabled during Super IO configuration) are
decoded by the LPC core.
5.1.1.1.2 LPC Memory Decoding
The LPC interface never responds to LPC memory accesses.
Table 5-3 LPC I/O Register Map Overview
Base Address Address Size Address Range Name Description
0x4E 2 SIW Super IO Configuration Registers
for Index and Date
0x80 1 POSTCODE POST Code Register
BASE1 8 COM1 UART1. Serial Port 1 (Logical Device
4). BASE1 address is set up during
Super IO Configuration.
BASE2 8 COM2 UART2. Serial Port 2. (Logical
Device 4). BASE2 address is set up
during Super IO Configuration.
0x600 128 REGISTERS FPGA Registers