Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 146)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 146
5.1.12.9 IPMC Interrupt Status Register
The IPMC Interrupt Status Register stores the IPMC interrupt event. The event is cleared by
IMPC with write one to clear.
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
5 Reserved 0 r
6 PCH_PLTRST_ reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
7 IPMC_RST_ REQ_ Payload Reset from IPMC.
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
Table 5-60 IPMC Reset Source Register (continued)
Address Offset: 0x17
Bit Description Default Access
IPMC version 1.2.0018 or higher is needed to clear the interrupt flag. Otherwise the IPMC
interrupt will always be active and produce infinite IPMC interrupts.
Table 5-61 IPMC Interrupt Status Register
Address Offset: 0x19
Bit Description Default Access
0 IPMC interrupt status
1: Platform Reset occurred (PCH_PLT_RST_) PWR_GOOD:0 IPMC: r/w1c
7:1 Reserved 0 r