Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 113)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 113
2:1 Interrupt priority level and source:
11: Receiver line status
10: Receiver data available
01: Transmitter holding register empty
00: Modem status 0 LPC: r
3 Time Out Detected:
0: No time out interrupt is pending
1: Character time-out indication (FIFO mode only) 0 LPC: r
5:4 Reserved 0 LPC: r
7:6 FIFO Mode Enable bits:
00: Default mode
01: Reserved
10: Reserved
11: FIFO mode 0 LPC: r
Table 5-28 Interrupt Identification Register (IIIR) (continued)
LPC IO Address: Base + 2
Bit Description Default Access
Table 5-29 Interrupt Identification Register Decode
Interrupt ID Interrupt Set/Reset Function
3:0 Priority Type Source Reset Control
0b0001 - None No Interrupt is pending -
0b0110 1 Receiver Line
Status Overrun Error, Parity Error, Framing Error,
Break Interrupt. Reading the Line Status
Register.
0b0100 2 Received
Data
Available. Non-FIFO mode: Receive Buffer is full. Non-FIFO mode: Reading
the Receiver Buffer Register.
FIFO mode: Trigger level was reached. FIFO mode: Reading bytes
until Receiver FIFO drops
below trigger level or setting
RESETRF bit in FCR register.
0b1100 Character
Timeout
indication. FIFO Mode only: At least 1 character is in
receiver FIFO and there was no activity for
a time period. Reading the Receiver FIFO or
setting RESETRF bit in FCR
register