3 power status register, Table 5-52, Power status register – Artesyn ATCA-7480 Installation and Use (February 2015) User Manual
Page 139: Maps and registers
Maps and Registers
ATCA-7480 Installation and Use (6806800T17A)
139
5.1.11.3 Power Status Register
This register provides some status information of external signals connected to the FPGA. The
content corresponds to the external signal level.
6
VCCIN CPU0 power good failure (signal
PWRGD_PVCCIN_CPU0):
0: No VCCIN CPU0 power issue.
1: VCCIN CPU0 power failure.
PWR_GOOD:0
IPMC: r
7
VCCIN CPU1 power good failure (signal
PWRGD_PVCCIN_CPU1):
0: No VCCIN CPU1 power issue.
1: VCCIN CPU1 power failure.
PWR_GOOD:0
IPMC: r
Table 5-51 Payload Power Failure Cause Register 3 (continued)
Address Offset: 0x0D
Bit
Description
Default
Access
Table 5-52 Power Status Register
Address Offset: 0x0E
Bit
Description
Default
Access
0
Status of signal SLP_A_.
Ext.
IPMC: r
1
Status of signal SLP_S4_.
Ext.
IPMC: r
2
Status of signal SLP_S3_.
Ext.
IPMC: r
3
Reserved
0
IPMC: r
4
Status of signal CPU_PWRGD
Ext.
IPMC: r
5
Status of signal XDP_HOOK1_SEL
Ext.
IPMC: r
6
Status of signal XDP_PWRGD_RST_
Ext.
IPMC: r
7
Status of signal XDP_CPU_SYSPWROK
Ext.
IPMC: r