Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 123)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 123
5.1.4.2.10 Scratch Register (SCR)
This 8-bit read/write register has no effect on the UART. It is intended as a scratch pad register
for use by the programmer.
5.1.4.3 Programmable Baud Rate Generator
The UART contains a programmable Baud Rate Generator that is capable of taking the
UART_CLK
input and dividing it by any divisor from 1 to (2 16- 1). The output frequency of the
Baud Rate Generator is 16 times the baud rate. Two 8-bit latches store the divisor in a 16-bit
binary format. These divisor latches must be loaded during initialization to ensure proper
operation of the Baud Rate Generator. If both divisor latches are loaded with 0, the 16X output
clock is stopped. Upon loading either of the divisor latches, a 16-bit baud counter is
immediately loaded. This prevents long counts on initial load. Access to the divisor latch can be
done with a word write.
6 Complement of the ring indicator (RI#) input
When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this
bit is equal to the MCR bit 2 (OUT1#). Not supported. Ext. LPC: r
7 Complement of the data carrier detect (DCD#) input
When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this
bit is equal to the MCR bit 3 (OUT2#). Not supported. Ext. LPC: r
Table 5-34 Modem Status Register (MSR) (continued)
LPC IO Address: Base + 6
Bit Description Default Access
Table 5-35 Scratch Register (SCR)
LPC IO Address: Base + 7
Bit Description Default Access
7:0 Scratch Register (SCR)
The scratch register is an 8 bit register that is intended for the
programmer's use as a scratch pad in the sense that it temporarily
holds the programmer's data without affecting any other ACE
operation. Undef. LPC: r/w