Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 145)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 145
5.1.12.8 IPMC Reset Source Register
The IPMC Reset Source Register stores the source of the most recent reset. A “1” in the register
bit indicates that the associated reset has occurred. If more than one reset occurs from
different sources without clearing the corresponding register bits, one cannot determine the
most recent reset source since more than one bit will be set. The same situation will happen if
two reset sources go active at the same time.
Table 5-59 IPMC Watchdog Timeout Register
Address Offset: 0x16
Bit Description Default Access
0 IPMC Watchdog Timeout:
0: No IPMC Watchdog Timeout
1: IPMC Watchdog Timeout occurred PWR_GOOD:0 IPMC: r/w
1 IPMC Pre-Timeout
0: No IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred PWR_GOOD:0 IPMC: r/w
7:2 Reserved 0 r
Table 5-60 IPMC Reset Source Register
Address Offset: 0x17
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 IPMC: r/w1c
1 XDPx reset request (Any one of XDPx signal
caused reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 IPMC: r/w1c
3 Reserved 0 r