Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 160)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 160
A write access to the RTM SPI Address/Command Register starts the SPI transaction. The write
cycle terminates when SPI transaction is finished.
A write access to the RTM SPI Address/Command Register with the Command Bit 0 (Write)
starts a SPI write transaction. The data byte in the SPI Write Register is written to the SPI device.
A write access to the RTM SPI Address/Command Register with the Command Bit 1 (Read)
starts a SPI read transaction. This contains the data read from the SPI device.
Table 5-79 RTM SPI Address/Command Register
Address Offset: 0x42
Bit Description Default Access
0 Command Bit
0: Write
1: Read 0 LPC: r/w
7:1 RTM SPI Address bits [6:0] 0 LPC: r/w
Table 5-80 RTM SPI Write Register
Address Offset: 0x43
Bit Description Default Access
7:0 RTM SPI write data - LPC: w
Table 5-81 RTM SPI Read Register
Address Offset: 0x43
Bit Description Default Access
7:0 RTM SPI read data 0 LPC: r