11 dimm adr status register, 13 cpu control register, 11dimm adr status register – Artesyn ATCA-7480 Installation and Use (February 2015) User Manual
Page 148: Table 5-63, Dimm adr status register, Table 5-64, Cpu control register, Maps and registers
Maps and Registers
ATCA-7480 Installation and Use (6806800T17A)
148
5.1.12.11 DIMM ADR Status Register
BIOS can read the status of PCH_ADR_IRQ_ signal from this register on boot up. This gives BIOS
the information that the DIMM has data stored from last boot. BIOS must clear this register
after boot up. Writing “1” to this register bit clears the register bit.
5.1.13 CPU Control Register
Table 5-63 DIMM ADR Status Register
Address Offset: 0x1A
Bit
Description
Default
Access
0
Indicates if the ADR feature is enabled. (GPIO37 of
Cavecreek)
0: ADR disabled (PCH_ADR_IRQ_ is driven high)
1: ADR enabled (PCH_ADR_IRQ_ is driven low)
PWR_GOOD:0
LPC: r/w1c
IPMC: r
7:1
Reserved 0
r
Table 5-64 CPU Control Register
Address Offset: 0x1E
Bit
Description
Default
Access
0
PCH_PSTATE_ pulse generation. Minimum low pulse width is Xμs
0: No action
1: Generate PSTATE low pulse.
-
IPMC: w
1
PCH_RCIN_ pulse generation. Minimum low pulse width is Xμs:
0: No action
1: Generate RCIN low pulse.
-
IPMC: w
7:2
Reserved -
-