25 cpu presence detection register, 26 cpu error status register, Table 5-88 – Artesyn ATCA-7480 Installation and Use (February 2015) User Manual
Page 164: Cpu presence detection register, Table 5-89, Cpu error status register, Maps and registers
Maps and Registers
ATCA-7480 Installation and Use (6806800T17A)
164
5.1.25 CPU Presence Detection Register
5.1.26 CPU Error Status Register
Table 5-88 CPU Presence Detection Register
Address Offset: 0x54
Bit
Description
Default
Access
1:0
Reserved
0
r
2
CPU0 Presence Detection (Status of signal
CPU0_SKTOCC_)
0: CPU present in socket
1: CPU not present. Socket is empty
Ext.
r
3
CPU1 Presence Detection (Status of signal
CPU1_SKTOCC_)
0: CPU present in socket
1: CPU not present. Socket is empty
Ext.
r
7:4
Reserved
0
r
Table 5-89 CPU Error Status Register
Address Offset: 0x57
Bit
Signal
Description
Default
Access
0
CPU_ERR_[0] CPU Error status signals.
Bit 0 = Non critical Error
Bit 1 = Non-fatal error (operating system or
firmware action required to contain and recover)
Bit 2 = Fatal error (system reset likely required to
recover)
Ext.
r
1
CPU_ERR_[1]
Ext.
r
2
CPU_ERR_[2]
Ext.
r
7:3
-
Reserved
0
r