Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 140)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 140
5.1.12 Reset Registers
5.1.12.1 BIOS Reset Source Register
The BIOS Reset Source Register stores the source of the most recent reset. A “1” in the register
bit indicates that the associated reset has occurred. If more than one reset occurs from
different sources without clearing the corresponding register bits, one cannot determine the
most recent reset source since more than one bit will be set. The same situation will happen if
two reset sources go active at the same time.
OS should never write to this register.
Table 5-53 BIOS Reset Source Register
Address Offset: 0x10
Bit Description Default Access
0 PWR_GOOD Payload Power-on reset
1: Reset occurred PWR_GOOD:1 LPC: r/w1c
IPMC: r
1 XDPx reset request (Any one of XDPx signal caused reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
2 PB_RST_ face plate push button reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
3 Reserved 0 r
4 RTM_PB_RST_ Reset key at RTM
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
5 Reserved 0 r
6 PCH_PLTRST_ reset
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
7 IPMC_RST_ REQ_ Payload Reset from IPMC.
1: Reset occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r