Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 141)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 141
5.1.12.2 Reset Mask Register
The reset mask register enables or disables forwarding of a reset source to reset output signal.
Only Push Button Resets requests are masked using the reset mask register. The register
default values are latched when PWR_GOOD is asserted. This register can be read or written by
the host CPU. A “1” in the register bit indicates that the associated reset is enabled. A “0”
indicates that the associated reset source is masked.
5.1.12.3 BIOS IPMC Watchdog Timeout Register
When one of the IPMC Watchdog Timeout bit of IPMC Watchdog Timeout Register is set, the
corresponding BIOS IPMC Watchdog Timeout bit is set. The BIOS clears this status bit by
writing one.
Table 5-54 Reset Mask Register
Address Offset: 0x11
Bit Description Default Access
1:0 Reserved 0 r
2 PB_RST_ face plate push button reset
1: enabled
0: disabled Ext.: FACE_PB_EN
1: (SW2.4 is OFF)
0: (SW2.4 is ON) LPC: r/w
3 Reserved 0 r
4 RTM_PB_RST_ Reset key at RTM
1: enabled
0: disabled Ext.: FACE_PB_EN
1: (SW2.4 is OFF)
0: (SW2.4 is ON) LCP: r/w
7:5 Reserved 0 r
OS should never write to this register.