Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 321)

IPMI Feature Set
ATCA-7480 Installation and Use (6806800T17A) 321
In case both SPI flashes are corrupted, the IPMC enters remote crisis recovery mode and moves
to hot-swap state M1, waiting for a FPGA firmware upgrade initiated from the ShMM.
To ensure that there is no possibility to accidentally overwrite both FPGA flashes with wrong
images not working, FPGA Fail Protect is implemented such that the active FPGA bank is
protected always by de-selecting it (only the backup firmware bank can be upgraded).
When the Fail Protect logic is triggered as a result of the timer expiry, a System Firmware
Progress event is logged as follows:
Sensor Type: 0x0F (System Firmware Progress)
Event Reading Type Code: 0x6F (Sensor Specific)
Event Data Byte 1: 0xA1 (System Firmware Hang)
Event Data Byte 2: 0x00 (CPU instance)
Event Data Byte 3: 0xXX (Failed Boot Bank ID: 0=Bank A; 1=Bank B)
Payload software is able to detect when Fail Protect was activated during last boot. For details,
see
Table 8-26 .
By default, Fail Protect is activated.
9.13.3 Remote Crisis Recover Mode
This mode is entered when both FPGA flashes are corrupted and the FPGA cannot be loaded.
The IPMC moves into hot-swap state M1 and waits for subsequent firmware upgrades initiated
from ShMM.
9.14 Settable Graceful Shutdown Timeout
The IPMI command, Set/Get System Boot Options together with the OEM parameter
#98 can be used to specify the timeout for Graceful Shutdown persistently. For details, see
System Boot Options Commands on page 233 .
By default, Graceful Shutdown persistently value is set to 10 seconds.