Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 221)

BIOS
ATCA-7480 Installation and Use (6806800T17A) 221
A9h QPI Initialization: Program final IO SAD setting
AAh QPI Initialization: Protocol layer and other Uncore settings
ABh QPI Initialization: Transition links to full speed operation
ACh QPI Initialization: Phy layer settings
ADh QPI Initialization: Link layer settings
AEh QPI Initialization: Coherency Settings
AFh QPI Initialization: QPI is done
B0h Memory Initialization: DIMM Detect
B1h Memory Initialization: Clock
B2h Memory Initialization: Read SPD data
B3h Memory Initialization: Early Init
B4h Memory Initialization: Rank Detection
B5h Memory Initialization: Early Channel Init
B6h Memory Initialization: JEDEC Init
B7h Memory Initialization: Channel Training
B8h Memory Initialization: Throttling Init
B9h Memory Initialization: BIST
BAh Memory Initialization: Init
BBh Memory Initialization: DDR Memory Mapping
BCh Memory Initialization: RAS Configuration
BDh Memory Initialization: Get Margins
BFh Memory Initialization: MRC Done
Table 6-20 BIOS POST Codes (continued)
POST Code Description