Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 215)

BIOS
ATCA-7480 Installation and Use (6806800T17A) 215
For debugging purpose, the POST Codes can be printed to the serial console by setting DIP
Switch 4-3 and 4-4 to ON.
Table 6-20 BIOS POST Codes
POST Code Description
02h Patching CPU microcode
03h Setup Cache as RAM
04h PCIE MMIO Base Address initial
05h CPU Generic MSR initial
06h Setup CPU speed
07h Cache as RAM test
08h Tune CPU frequency ratio to maximum level
09h Setup BIOS ROM cache
0Ah Enter Boot Firmware Volume
70h Super I/O initial
71h CPU Early Initial
72h Multi-processor Early initial
73h HyperTransport initial
74h PCIE MMIO BAR Initial
75h North Bridge Early Initial
76h South Bridge Early Initial
77h PCIE Training
78h TPM Initial
79h SMBUS Early Initial
7Ah Clock Generator Initial
7Bh Internal Graphic device early initial, PEI_IGDOpRegion
7Ch HECI Initial
7Dh Watchdog timer initial
7Eh Memory Initial for Normal boot
7Fh Memory Initial for Crisis Recovery