Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 171)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 171
5.1.29 IPMC BIOS Communication Registers
5.1.30 Scratch Registers
Table 5-102 IPMC BIOS Communication Register 1
Address Offset: 0x7A
Bit Description Default Access
7:0 IPMC BIOS Communication bits PWR_GOOD:0 LPC: r/w
IPMC: r/w
Table 5-103 IPMC BIOS Communication Register 2
Address Offset: 0x7B
Bit Description Default Access
7:0 IPMC BIOS Communication bits PWR_GOOD:0 LPC: r/w
IPMC: r/w
Table 5-104 IPMC BIOS Communication Register 3
Address Offset: 0x7C
Bit Description Default Access
7:0 IPMC BIOS Communication bits PWR_GOOD:0 LPC: r/w
IPMC: r/w
Table 5-105 LPC Scratch Register
Address Offset: 0x7D
Bit Description Default Access
7:0 LPC Scratch bits. PWR_GOOD:0 LPC: r/w
IPMC: r