Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 308)

IPMI Feature Set
ATCA-7480 Installation and Use (6806800T17A) 308
The power failing state is maintained until Payload power is turned off.
 Manual Powering: Setting the switch SW 100. 1 from ON to OFF
 IPMC Controlled Powering: The IPMC shutting down the payload power (signal
IPMC_VP48_EN_ is deserted).
For more information, see
Table 5-47 .
For all possible failing states and their coding, see Table 5-48 . When the board is powered via
switch SW100.1, the debug mode is enabled, where some timeouts are disabled.
9.3.10 Payload Power Failure Cause Sensor
The IPMC uses three sensors to monitor the power failure cause of the payload domain. Table
5-49 gives more details about the payload power failure. The Payload Power Failure Registers 1
to 3 are always 0 when the Payload Power Failure status (bit 7) is not set.
The Payload Power Failure Cause Register 2 covers the main board voltages. For more
information, see
Table 5-50 .
The Payload Power Failure Cause Register 3 covers CPU specific voltages. When a CPU is not
mounted (detected via CPU0_SKTOCC_ and CPU1_SKTOCC_) the corresponding power
failure bits will never be set. For more information, see
Table 5-51 .
9.4 POST
POST is executed at IPMC startup when either a hard (blade physically extracted/reinserted) or
a cold (IPMI Command) reset is performed. POST verifies the functionality of SRAM, IPMB-0,
EEPROM data storage, FRU-Information, and all devices (primarily sensors) attached to the
IPMC's private master-only I2C bus. A detailed description of POST tests are as follows:
 FRU-InformationU - Verifies that the FRU-Information is readable from the external
EEPROM where it is stored. Once read, each section's checksum is computed and
validated.
 IPMB-0U - Reads the ready signals coming from the I2C buffers. If this test passes, both
ready signals are active and both IPMB busses (IPMB-A and IPMB-B) are enabled.