Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 170)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 170
5.1.28 BIOS Version Registers
Table 5-98 Telecom Clock Monitor Upper Limit Register
Address: 0x69 -0x6A
Bit Description Default Access
15:0 Upper Limit for supervised Telecom Clock:
Used by
Table 5-93 Telecom Clock Monitor Out of Range
Register.
0xFFFF LPC: r/w
Table 5-99 BIOS Version Register 1
Address Offset: 0x74
Bit Description Default Access
7:0 BIOS Version bits 0 to 7 0 LPC: r/w
IPMC: r
Table 5-100 BIOS Version Register 2
Address Offset: 0x75
Bit Description Default Access
7:0 BIOS Version bits 8 to 15 0 LPC: r/w
IPMC: r
Table 5-101 BIOS Version Register 3
Address Offset: 0x76
Bit Description Default Access
7:0 BIOS Version bits 16 to 23 0 LPC: r/w
IPMC: r