Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 318)

IPMI Feature Set
ATCA-7480 Installation and Use (6806800T17A) 318
When the Failsafe logic is triggered as a result of the BMC Watchdog timeout, a System
Firmware Progress event is logged as follows:
Sensor Type: 0x0F (System Firmware Progress)
Event Reading Type Code: 0x6F (Sensor Specific)
Event Data Byte 1: 0xA1 (System Firmware Hang)
Event Data Byte 2: 0x00 (CPU instance)
Event Data Byte 3: 0xXX (Failed Boot Bank ID: 0=Bank A; 1=Bank B)
The Failsafe logic makes three attempts to boot the payload successfully. After three attempts,
the Failsafe logic is automatically disabled and the boot bank is left in the original state (before
the payload was booted).
Payload software is able to detect when failsafe was activated during last boot. For details, see
Table 8-26 .
By default, Failsafe is disabled.
9.13 Glue Logic FPGA Flash Selection
The ATCA-7480 provides redundant FPGA flashes for both manual and automatic crisis
recoveries.
The general concept is that there is always an active and a standby SPI flash device. The role of
these two devices can be reversed by the IPMC; for this to work, the IPMC has to drive the chip
select signals to the SPI flashes. The final decision about which of the two devices is active and
standby is made by the IPMC.
Due to the fact that the Glue Logic FPGA is powered by management power, the IPMC needs
to control the Glue Logic FPGA during power-up.
The FPGA Bank selection is implemented such that swapping the SPI flashes is in effect
immediately. Nevertheless due to the FPGA is already loaded during power-up, the SPI flash
selection does not enforce the FPGA to reload. Furthermore, in case of the payload, powered
(M4) FPGA cannot be loaded neither.
Therefore, swapping FPGA bank is possible only with the following steps:
1. Swap the FPGA banks
2. Power-cycle the payload