Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 121)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 121
5.1.4.2.9 Modem Status Register (MSR)
This 8-bit register provides the current state of the control lines from the modem or data set (or
a peripheral device emulating a modem) to the processor. In addition to this current state
information, four bits of the Modem Status Register provide change information. Bits 03:00 are
set to a logic 1 when a control input from the Modem changes state. They are reset to a logic 0
when the processor reads the Modem Status Register.
6 Transmitter Empty (TEMT) indicator
TEMT bit is set when the THR and the TSR are both empty. When
either the THR or the TSR contains a data character, TEMT is cleared.
In the FIFO mode, TEMT is set when the transmitter FIFO and shift
register are both empty:
1: THR/Transmit FIFO/TSR empty
0: THR/Transmit FIFO/TSR contains data 1 LPC: r
7 FIFO data error
In the FIFO mode, LSR7 is set when there is at least one parity,
framing, or break error in the FIFO. It is cleared when the
microprocessor reads the LSR and there are no subsequent errors in
the FIFO. If FIFO is not used, bit always reads 0:
1: FIFO data error encountered
0: No FIFO error encountered 0 LPC: r
Table 5-33 Line Status Register (LSR) (continued)
LPC IO Address: Base + 5
Bit Description Default Access