Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 114)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 114
5.1.4.2.5 FIFO Control Register (FCR)
FCR is a write-only register that is located at the same address as the IIR (IIR is a read-only
register). FCR enables/disables the transmitter/receiver FIFOs, clears the transmitter/receiver
FIFOs, and sets the receiver FIFO trigger level.
0b0010 3 Transmit
FIFO Data
Request Non-FIFO mode: Transmit Holding
Register Empty Reading the IIR Register (if
the source of the interrupt)
or writing into the Transmit
Holding Register.
FIFO mode: Transmit FIFO has half or less
than half data. Reading the IIR Register (if
the source of the interrupt)
or writing to the Transmitter
FIFO.
0b0000 4 Modem
Status Clear to Send, Data Set Ready, Ring
Indicator, Received Line Signal Detect Reading the modem status
register
Table 5-29 Interrupt Identification Register Decode (continued)
Interrupt ID Interrupt Set/Reset Function
3:0 Priority Type Source Reset Control
Table 5-30 FIFO Control Register (FCR)
LPC IO Address: Base + 2
Bit Description Default Access
0 FIFO enable/disable:
1: Transmitter and Receiver FIFO enabled
0: FIFO disabled 0 LPC: w
1 Receiver FIFO reset:
1: Bytes in receiver FIFO and counter are reset. Shift register is not
reset (bit is self-clearing)
0: No effect 0 LPC: w
2 Transmit FIFO reset:
1: Bytes in receiver FIFO and counter are reset. Shift register is not
reset (bit is self-clearing)
0: No effect 0 LPC: w
3 Receiver/Transmitter ready. Not supported. 0 LPC: w