Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 147)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 147
5.1.12.10 DIMM ADR Configuration Register
The DIMM ADR Configuration Register enables or disables the ADR feature. Each bit of this
register corresponds to a reset source. When a bit is set, it enables the ADR for the
corresponding reset signal. Upon receiving a reset event, FPGA reset logic looks if the ADR is
enabled for that particular reset. When enabled, PCH_ADR_IRQ_ signal is asserted. When PCH
signals completion with assertion of ADR_COMPLETE the Reset State Machine asserts
PCH_SYS_RST_. If ADR is not enabled PCH_SYS_RST_ is generated immediately without the
assertion of PCH_ADR_IRQ_ signal.
Table 5-62 DIMM ADR Feature Configuration Register
Address Offset: 0x18
Bit Description Default Access
0 ADR enable for Push button reset
1: ADR enabled
0: ADR disabled PWR_GOOD:0 LPC: r/w
IPMC: r
1 ADR enable for RTM Push button reset
1: ADR enabled
0: ADR disabled PWR_GOOD:0 LPC: r/w
IPMC: r
2 ADR enable for IPMI reset
1: ADR enabled
0: ADR disabled PWR_GOOD:0 LPC: r/w
IPMC: r
7:3 Reserved 0 r