Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 166)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 166
When at least one bit of the Table 5-91 is set, the corresponding status bit
CLK_MONITOR_FINISHED of the Table 5-69 is also set.
When at least one bit of the Table 5-93 is set, the corresponding status bit
CLK_MONITOR_OUT_OF_RANGE of Table 5-69 is also set.
Table 5-92 Telecom Clock Monitor Status Register
Address: 0x61
Bit Description Default Access
3:0 Result available for supervised Telecom Clock 0 to 3.
Corresponding bit is set when measurement has
finished.
Clearing bit triggers new measurement. 0 LPC: r/w1c
7:4 Reserved 0 r
Table 5-93 Telecom Clock Monitor Out of Range Register
Address: 0x62
Bit Description Default Access
3:0 Frequency of supervised Telecom Clock 0 to 3 is out of range.
Gate Mode:
Corresponding bit is set when the number of positive Clock
edges within the selected time base is:
< Lower limit or
> Upper limit
Period Mode:
Corresponding bit is set when the Clock 0 Period within the
selected time base is:
< Lower limit or
> Upper limit
Clearing bit triggers new sequence of measurements. 0 LPC: r/w1c
7:4 Reserved 0 r