Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 116)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 116
3 Parity enable/disable
When bit 3 is set, a parity bit is generated in transmitted data
between the last data WORD bit and the first stop bit. In
received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.:
1: Parity enabled
0: Parity disabled 0 LPC: r/w
4 Parity even/odd
When parity is enabled and bit 4 is set, even parity (an even
number of logic ones in the data and parity bits) is selected.
When parity is disabled and bit 4 is cleared, odd parity (an odd
number of logic ones) is selected.:
1: Even parity
0: Odd parity 0 LPC: r/w
5 Stick parity
When bits 3, 4, and 5 are set, the parity bit is transmitted and
checked as cleared. When bits 3 and 5 are set and bit 4 is
cleared, the parity bit is transmitted and checked as set. If bit
5 is cleared, stick parity is disabled.:
1: Stick parity enabled
0: Stick parity disabled 0 LPC: r/w
6 Break control bit
Bit 6 is set to force a break condition, i.e. a condition where
TXD is forced to the spacing (cleared) state. When bit 6 is
cleared, the break condition is disabled and has no affect on
the transmitter logic. It only effects TXD:
1: Break condition enabled
0: Break condition disabled 0 LPC: r/w
7 Divisor latch access bit (DLAB)
Bit 7 must be set to access the divisor latches of the baud
generator during a read or write. Bit 7 must be cleared during
a read or write to access the RBR, THR, or IER.:
1: Access to DLL and DLM registers
0: Access to RBR, THR and IER registers 0 LPC: r/w
Table 5-31 Line Control Register (LCR) (continued)
LPC IO Address: Base + 3
Bit Description Default Access