Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 144)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 144
When one of the IPMC Watchdog Timeout bits of IPMC Watchdog Timeout Register is set, the
corresponding OS IPMC Watchdog Timeout Register bit is set. The OS clears this status bit by
writing one.
5.1.12.7 IPMC Watchdog Timeout Register
The IPMC SW sets the corresponding bit to signal of an IPMC watchdog timeout event. When
the IPMC Watchdog Timeout bit is set from low to high, the corresponding bits in
Table 5-55
and Table 5-58 are set.
BIOS should never write to this register.
Table 5-58 OS IPMC Watchdog Timeout Register
Address Offset: 0x15
Bit Description Default Access
0 OS IPMC Watchdog Timeout:
1: IPMC Watchdog Timeout occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
1 OS IPMC Pre-Timeout
1: IPMC Pre-Timeout occurred PWR_GOOD:0 LPC: r/w1c
IPMC: r
7:2 Reserved 0 r
IPMC needs to clear the IPMC watchdog timeout bit to arm IPMC watchdog timeout event
recognition.